View LT1761_4447650.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

lt3032 series 1 3032fd typical application features description dual 150ma positive/negative low noise low dropout linear regulator the lt ? 3032 is a dual, low noise, positive and negative low dropout voltage linear regulator. each regulator delivers up to 150ma with a typical 300mv dropout voltage. each regulators quiescent current is low (30a operating and <3a in shutdown) and well-controlled in dropout, making it an excellent choice for battery-powered circuits. another key feature of the lt3032 is low output noise. adding an external 10nf bypass capacitor to each regulator reduces output noise to 20v rms/ 30v rms over a 10hz to 100khz bandwidth. the lt3032 is stable with minimum output capacitors of 2.2f. the regulators do not require the addition of esr as is common with other regulators. the regulators are offered as adjustable output devices with an output voltage down to the 1.22v reference volt- age or in ? xed voltages of 5v, 12v and 15v. internal protection circuitry includes reverse-output protection, current limiting and thermal limiting. the lt3032 is available in a unique low pro? le 14-lead 4mm 3mm 0.75mm dfn package with exposed back- side pads for each regulator, allowing optimum thermal performance. dual polarity low noise 150ma power supply applications n low noise: 20v rms (positive) and 30v rms (negative) n low quiescent current: 30a/channel n wide input voltage range: 2.3v to 20v n output current: 150ma n low shutdown current: <3a total (typical) n low dropout voltage: 300mv/channel n fixed output voltages: 5v, 12v, 15v n adjustable outputs from 1.22v to 20v n no protection diodes needed n stable with 2.2f output capacitors n stable with ceramic, tantalum or aluminum capacitors n starts into reverse output voltage n current limit and thermal limit n low pro? le 14-lead 4mm 3mm 0.75mm dfn package n battery-powered instruments n bipolar power supplies n low noise power supplies l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks and thinsot is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. 10f 10f 10f 0.01f 0.01f 10f 5.4v to 20v 5v out at 150ma 20v rms noise C5v out at C150ma 30v rms noise C5.4v to C20v <0.25v = off >2v = on shdnp shdnn outp inp inn lt3032-5 bypp gnd bypn outn 3032 ta01 outp 100v/div outn 100v/div 20v rms 30v rms 1ms/div 3032 ta02a 10hz to 100khz output noise
lt3032 series 2 3032fd pin configuration absolute maximum ratings inp pin voltage .......................................................20v inn pin voltage .......................................................20v outp pin voltage....................................................20v outn pin voltage (note 3) .....................................20v inp pin to outp pin differential voltage ................20v outn pin to inn pin differential voltage (note 3) ..........................................................C0.5v, 20v adjp pin voltage ......................................................7v adjn pin voltage (with respect to inn pin, note 3) ..................C0.5v, 20v bypp pin voltage ...................................................0.5v bypn pin voltage (with respect to inn pin) ........................................20v shdnp pin voltage .................................................20v shdnn pin voltage (with respect to inn pin, note 3) ..................C0.5v, 35v shdnn pin voltage (with respect to gnd pin) ..............................C20v, 15v output short-circuit duration .......................... inde? nite operating junction temperature range (note 2) e, i grades ......................................... C40c to 125c mp-grade .......................................... C55c to 125c storage temperature range .................. C65c to 150c (note 1) 1 2 3 4 5 6 7 14 13 12 11 10 9 8 inp nc shdnp bypn shdnn inn adjn/nc ? ? outp nc ? /adjp bypp gnd gnd inn outn top view de14ma package 14-lead (4mm 3mm) plastic dfn 15 gnd 16 inn t jmax = 125c, ja = 30c/w to 43c/w*, jc = 10c/w* *see applications information for more detail ? pin 2: nc for lt3032-5/lt3032-12/lt3032-15, adjp for lt3032 ?? pin 8: nc for lt3032-5/lt3032-12/lt3032-15, adjn for lt3032 exposed pad (pin 15) is gnd, must be soldered to pins 4, 5 on pcb exposed pad (pin 16) is inn, must be soldered to pins 6, 9 on pcb order information lead free finish tape and reel part marking* package description temperature range lt3032ede#pbf lt3032ede#trpbf 3032 14-lead (4mm 3mm) plastic dfn C40c to 125c lt3032ide#pbf lt3032ide#trpbf 3032 14-lead (4mm 3mm) plastic dfn C40c to 125c lt3032mpde#pbf lt3032mpde#trpbf 3032 14-lead (4mm 3mm) plastic dfn C55c to 125c lt3032ede-5#pbf lt3032ede-5#trpbf 30325 14-lead (4mm 3mm) plastic dfn C40c to 125c lt3032ide-5#pbf lt3032ide-5#trpbf 30325 14-lead (4mm 3mm) plastic dfn C40c to 125c lt3032mpde-5#pbf lt3032mpde-5#trpbf 30325 14-lead (4mm 3mm) plastic dfn C55c to 125c lt3032ede-12#pbf lt3032ede-12#trpbf 30322 14-lead (4mm 3mm) plastic dfn C40c to 125c lt3032ide-12#pbf lt3032ide-12#trpbf 30322 14-lead (4mm 3mm) plastic dfn C40c to 125c lt3032mpde-12#pbf lt3032mpde-12#trpbf 30322 14-lead (4mm 3mm) plastic dfn C55c to 125c lt3032ede-15#pbf lt3032ede-15#trpbf 03215 14-lead (4mm 3mm) plastic dfn C40c to 125c lt3032ide-15#pbf lt3032ide-15#trpbf 03215 14-lead (4mm 3mm) plastic dfn C40c to 125c lt3032mpde-15#pbf lt3032mpde-15#trpbf 03215 14-lead (4mm 3mm) plastic dfn C55c to 125c
lt3032 series 3 3032fd electrical characteristics parameter conditions min typ max units minimum inp operating voltage lt3032 i load = 150ma l 1.8 2.3 v minimum inn operating voltage lt3032 i load = C150ma l C2.3 C1.6 v regulated output voltage (notes 4, 10) lt3032-5 v inp = 5.5v, i load = 1ma 6v v inp 20v, 1ma i load 150ma l 4.925 4.850 5.00 5.00 5.075 5.150 v v lt3032-5 v inn = C5.5v, i load = C1ma C6v v inn C20v, C1ma i load C150ma l C5.075 C5.150 C5.00 C5.00 C4.925 C4.850 v v lt3032-12 v inp = 12.5v, i load = 1ma 13v v inp 20v, 1ma i load 150ma l 11.82 11.64 12.00 12.00 12.18 12.36 v v lt3032-12 v inn = C12.5v, i load = C1ma C13v v inn C20v, C1ma i load 150ma l C12.18 C12.36 C12.00 C12.00 C11.82 C11.64 v v lt3032-15 v inp = 15.5v, i load = 1ma 16v v inp 20v, 1ma i load 150ma l 14.775 14.550 15.00 15.00 15.225 15.450 v v lt3032-15 v inn = C15.5v, i load = C1ma C16v v inn C20v, C1ma i load 150ma l C15.225 C15.450 C15.00 C15.00 C14.775 C14.550 v v adjp pin voltage (notes 4, 5) lt3032 v inp = 2v, i load = 1ma 2.3v v inp 20v, 1ma i load 150ma l 1.202 1.184 1.22 1.22 1.238 1.256 v v adjn pin voltage (notes 4, 5, 10) lt3032 v inn = C2v, i load = C1ma C2.3v v inn C20v, C1ma i load C150ma l C1.238 C1.256 C1.22 C1.22 C1.202 C1.184 v v line regulation (note 5) lt3032-5 outp v inp = 5.5v to 20v, i load = 1ma outn v inn = C5.5v to C20v, i load = C1ma l l 1 15 6 50 mv mv lt3032-12 outp v inp = 12.5v to 20v, i load = 1ma outn v inn = C12.5v to C20v, i load = C1ma l l 1.5 13 15 75 mv mv lt3032-15 outp v inp = 15.5v to 20v, i load = 1ma outn v inn = C15.5v to 20v, i load = C1ma l l 2 10 20 75 mv mv lt3032 adjp v inp = 2v to 20v, i load = 1ma adjn v inn = C2v to C20v, i load = C1ma l l 1 1 6 12 mv mv the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. lead based finish tape and reel part marking* package description temperature range lt3032ede lt3032ede#tr 3032 14-lead (4mm 3mm) plastic dfn C40c to 125c lt3032ide lt3032ide#tr 3032 14-lead (4mm 3mm) plastic dfn C40c to 125c lt3032mpde lt3032mpde#tr 3032 14-lead (4mm 3mm) plastic dfn C55c to 125c lt3032ede-5 lt3032ede-5#tr 30325 14-lead (4mm 3mm) plastic dfn C40c to 125c lt3032ide-5 lt3032ide-5#tr 30325 14-lead (4mm 3mm) plastic dfn C40c to 125c lt3032mpde-5 lt3032mpde-5#tr 30325 14-lead (4mm 3mm) plastic dfn C55c to 125c lt3032ede-12 lt3032ede-12#tr 30322 14-lead (4mm 3mm) plastic dfn C40c to 125c lt3032ide-12 lt3032ide-12#tr 30322 14-lead (4mm 3mm) plastic dfn C40c to 125c lt3032mpde-12 lt3032mpde-12#tr 30322 14-lead (4mm 3mm) plastic dfn C55c to 125c lt3032ede-15 lt3032ede-15#tr 03215 14-lead (4mm 3mm) plastic dfn C40c to 125c lt3032ide-15 lt3032ide-15#tr 03215 14-lead (4mm 3mm) plastic dfn C40c to 125c lt3032mpde-15 lt3032mpde-15#tr 03215 14-lead (4mm 3mm) plastic dfn C55c to 125c consult ltc marketing for parts speci? ed with wider operating temperature ranges. *the temperature grade is identi? ed by a label on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speci? cations, go to: http://www.linear.com/tapeandreel/ order information
lt3032 series 4 3032fd parameter conditions min typ max units load regulation (notes 5, 13) lt3032-5 outp v inp = 6v, i load = 1ma to 150ma C9 mv lt3032-5 outn v inn = C6v, i load = C1ma to C150ma 15 mv lt3032-12 outp v inp = 13v, i load = 1ma to 150ma 20 mv lt3032-12 outn v inn = C13v, i load = C1ma to C150ma 20 mv lt3032-15 outp v inp = 16v, i load = 1ma to 150ma 25 mv lt3032-15 outn v inn = C16v, i load = C1ma to C150ma 27 mv lt3032 adjp v inp = 2.3v, i load = 1ma to 150ma v inp = 2.3v, i load = 1ma to 150ma l C1.5 C7 C15 mv mv lt3032 adjn v inn = C2.3v, i load = C1ma to C150ma v inn = C2.3v, i load = C1ma to C150ma l 1.5 7 15 mv mv dropout voltage v inp = v outp(nominal) (notes 6, 7) i load = 1ma l 0.09 0.20 v i load = 10ma l 0.15 0.27 v i load = 50ma 0.21 v i load = 150ma 0.27 v dropout voltage v inn = v outn(nominal) (notes 6, 7) i load = C1ma l 0.10 0.20 v i load = C10ma l 0.15 0.27 v i load = C50ma 0.21 v i load = C150ma 0.30 v gnd pin current v inp = v outp(nominal) , v inn = 0v (notes 6, 8, 9) i load = 0ma (lt3032, lt3032-5) i load = 0ma (lt3032-12, lt3032-15) i load = 1ma (lt3032, lt3032-5) i load = 1ma (lt3032-12, lt3032-15) i load = 10ma i load = 50ma i load = 150ma l l l l l l l C25 C50 C70 C80 C350 C1.3 C4 C65 C120 C120 180 C500 C1.8 C7 a a a a a ma ma gnd pin current v inn = v outn(nominal) , v inp = 0v (notes 6, 8, 9, 10) i load = 0ma (lt3032, lt3032-5) i load = 0ma (lt3032-12, lt3032-15) i load = C1ma (lt3032, lt3032-5) i load = C1ma (lt3032-12, lt3032-15) i load = C10ma i load = C50ma i load = C150ma l l l l l l l 30 50 85 90 300 0.75 2 70 130 180 180 600 1.5 5 a a a a a ma ma adjp pin bias current lt3032 (notes 5, 9) 30 100 na adjn pin bias current lt3032 (notes 5, 9) C30 C100 na shutdown threshold shdnp v outp = off to on shdnp v outp = on to off shdnn v outn = off to on (positive) shdnn v outn = off to on (negative) shdnn v outn = on to off (positive) shdnn v outn = on to off (negative) l l l l l l 0.25 C2.8 0.25 0.7 0.6 1.4 C1.9 1.4 C1.9 2 2 C0.25 v v v v v v shdnp pin current (note 9) v shdnp = 0v v shdnp = 20v C1 1 1 4 a a shdnn pin current (note 9) v shdnn = 0v v shdnn = 15v v shdnn = -15v C1 6 C3 1 15 C9 a a a quiescent current in shutdown v inp = 6v, v shdnp = 0v, v inn = 0v v inn = C6v, v shdnn = 0v, v inp = 0v (lt3032, lt3032-5) v inn = v out(nominal) C1v, v shdnn = 0v, v inp = 0v (lt3032-12/ lt3032-15) l l l 0.1 C3 10 8 C10 20 a a a electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c.
lt3032 series 5 3032fd electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the lt3032 is tested and speci? ed under pulse load conditions such that t j ? t a . the lt3032e is 100% tested at t a = 25c. performance of the lt3032e over the full C40c to 125c operating junction temperature range is assured by design, characterization, and correlation with statistical process controls. the lt3032i regulators are guaranteed over the full C40c to 125c operating junction temperature range. note 3: parasitic diodes exist internally between the inn pin and the outn, adjn, and shdnn pins. these pins cannot be pulled more than 0.5v below the inn pin during fault conditions, and must remain at a voltage more positive than the inn pin during operation. note 4: operating conditions are limited by maximum junction temperature. speci? cations do not apply for all possible combinations of input voltages and output currents. when operating at maximum input voltages, the output current ranges must be limited. when operating at maximum output currents, the input voltage ranges must be limited. note 5: the lt3032 is tested and speci? ed for these conditions with the adjp pin tied to the outp pin and the adjn pin tied to the outn pin. note 6: to satisfy requirements for minimum input voltage, the lt3032 is tested and speci? ed for these conditions with an external resistor divider (two 250k resistors) from outp/outn to the corresponding adjp/adjn pin to give an output voltage of 2.44v. the external resistor divider adds a 5a dc load on the output. the lt3032-12/lt3032-15 have higher internal resistor divider current, resulting in higher gnd pin current at light/no load. note 7: dropout voltage is the minimum input-to-output voltage differential needed to maintain regulation at a speci? ed output current. in dropout, output voltage equals: v inp/inn C v dropout for lower output voltages, dropout voltage is limited by the minimum input voltage speci? cation under some output voltage/load conditions; see curves for minimum inn voltage and minimum inp voltage in typical performance characteristics. ltc is unable to guarantee maximum dropout voltage speci? cations at 50ma and 150ma due to production test limitations with kelvin-sensing the package pins. please consult the typical performance characteristics for curves of dropout voltage as a function of output load current and temperature. note 8: gnd pin current is tested with v inp = v outp(nominal) or v inn = v outn(nominal) and a current source load. this means the device is tested while operating in its dropout region. this is the worst-case gnd pin current. gnd pin current decreases slightly at higher input voltages. note 9: positive current ? ow is into the pin. negative current ? ow is out of the pin. note 10: for input-to-output differential voltages from inn to outn greater than C7v, a C50a load is needed to maintain regulation. note 11: reverse output current is tested with the inp pin grounded and the outp pin forced to the nominal output voltage. this current ? ows into the outp pin and out the gnd pin. note 12: positive side current limit is tested at v inp = 2.3v or v outp(nominal) + 1v (whichever is more positive). negative side current limit is tested at v inn = C2.3v or v outn(nominal) C 1v (whichever is more negative). note 13: ltc is unable to guarantee load regulation speci? cations on ? xed voltage versions of the lt3032 due to production test limitations with kelvin-sensing the package pins. please consult the typical performance characteristics for curves of load regulation as a function of temperature. parameter conditions min typ max units output voltage noise (10hz to 100khz) c outp = 10f, c bypp 0.01f, i load = 150ma c outn = 10f, c bypn 0.01f, i load = C150ma 20 30 v rms v rms ripple rejection v ripple = 0.5v p-p, f ripple = 120hz v inp to v outp = 1.5v (average), i load = 100ma v inn to v outn = C1.5v (average), i load = C100ma 50 46 68 54 db db current limit (note 12) v inp = 7v, v outp = 0v v inn = C7v, v outn = 0v v inp = 2.3v or v outp(nominal) + 1v, v outp = C0.1v v inn = C2.3v or v outp(nominal) C 1v, v outn = 0.1v l l 170 170 400 350 ma ma ma ma inp reverse leakage current v inp = C20v, v outp = 0v l C1 ma inn reverse leakage current v inn = 20v, v outn , v adjn , v shdnn = open circuit l 1ma reverse output current (notes 5, 11) lt3032-5 lt3032-12 lt3032-15 lt3032 v outp = 5v, v inp < 5v v outp = 12v, v inp < 12v v outp = 15v, v inp < 15v v outp = v adjp = 1.22v, v inp < 1.22v 10 25 25 5 20 50 50 10 a a a a
lt3032 series 6 3032fd typical performance characteristics inn-to-outn dropout voltage inp quiescent current inn quiescent current inp-to-outp typical dropout voltage inn-to-outn typical dropout voltage inp-to-outp dropout voltage load current (ma) 500 450 400 350 300 250 200 150 100 50 0 dropout voltage (mv) 3032 g01 020 40 60 80 100 120 140 160 t j = 125c t j = 25c load current (ma) 0 500 450 400 350 300 250 200 150 100 50 0 3032 g02 C40 C80 C120 C160 dropout voltage (mv) t j = 125c t j = 25c temperature (c) C50 dropout voltage (mv) 0 50 75 3032 g03 C25 25 100 125 i l = 150ma i l = 50ma i l = 10ma i l = 1ma 500 450 400 350 300 250 200 150 100 50 0 temperature (c) C50 dropout voltage (mv) 0 50 75 3032 g04 C25 25 100 125 500 450 400 350 300 250 200 150 100 50 0 i l = 150ma i l = 10ma i l = 1ma i l = 50ma temperature (c) C50 quiescent current (a) 100 3032 g05 050 70 50 60 40 30 20 10 0 C25 25 75 125 i l = 0 (fixed voltages) i l = 5a (adjustable) v shdnp = v inp = 6v (5v, adj) v shdnp = v inp = v outp(nominal) +1v (12v, 15v) v shdnp = 0v, v inp = 6v temperature (c) C60 C50 C40 C30 C20 C10 0 3032 g06 quiescent current (a) i l = 0 (fixed voltages) i l = C5a (adjustable) C50 C25 0 25 50 75 100 125 v shdnn = v inn = v outn(nominal) C1v (12v, 15v) v shdnn = v inn = C6v (5v, adj) v shdnn = 0v, v inn = C6v lt3032-5 outp output voltage lt3032-5 outn output voltage lt3032-12 outp output voltage temperature (c) C50 outp output voltage (v) 100 3032 g52 050 5.100 5.075 5.050 5.025 5.000 4.975 4.950 4.925 4.900 C25 25 75 125 i l = 1ma temperature (c) C50 outn output voltage (v) 25 3032 g53 C25 0 50 C5.100 C5.075 C5.050 C5.025 C5.000 C4.975 C4.950 C4.925 C4.900 75 100 125 i l = C1ma temperature (c) C50 outp output voltage (v) 100 3032 g58 050 12.24 12.18 12.12 12.06 12.00 11.94 11.88 11.82 11.76 C25 25 75 125 i l = 1ma
lt3032 series 7 3032fd lt3032 adjp pin voltage temperature (c) C50 adjp pin voltage (v) 100 3032 g07 050 1.240 1.235 1.230 1.225 1.220 1.215 1.210 1.205 1.200 C25 25 75 125 i l = 1ma lt3032 adjn pin voltage temperature (c) C1.240 C1.235 C1.230 C1.225 C1.220 C1.215 C1.210 C1.205 C1.200 3032 g08 adjn pin voltage (v) i l = C1ma C50 C25 0 25 50 75 100 125 typical performance characteristics lt3032-5 inp quiescent current lt3032-5 inn quiescent current lt3032-12 inn quiescent current lt3032-12 inp quiescent current inp voltage (v) 0 inp quiescent current (a) 400 350 300 250 200 150 100 50 0 16 3032 g54 4 2 6 10 14 18 8 12 20 v shdnp = v inp t j = 25c r l = v shdnp = 0v inn voltage (v) C60 C50 C40 C30 C20 C10 C0 3032 g55 inn quiescent current (a) 0 C2 C4 C6 C8 C10 C12 C14 C16 C18 C20 t j = 25c r l = v shdnn = v inn v shdnn = 0v inp voltage (v) 0 inn quiescent current (a) C80 C70 C60 C50 C40 C30 C20 C10 0 C16 3032 g63 C4 C2 C6 C10 C14 C18 C8 C12 C20 t j = 25c r l = v shdnn = 0v v shdnn = v inn inp voltage (v) 0 inp quiescent current (a) 400 350 300 250 200 150 100 50 0 16 3032 g62 4 2 6 10 14 18 8 12 20 t j = 25c r l = v shdnp = 0v v shdnp = v inp temperature (c) C50 outp output voltage (v) 100 3032 g59 050 C12.24 C12.18 C12.12 C12.06 C12.00 C11.94 C11.88 C11.82 C11.76 C25 25 75 125 i l = C1ma lt3032-12 outn output voltage lt3032-15 outp output voltage lt3032-15 outn output voltage temperature (c) C50 outp output voltage (v) 100 3032 g60 050 15.300 15.225 15.150 15.075 15.000 14.925 14.850 14.775 14.700 C25 25 75 125 i l = 1ma temperature (c) C50 outn output voltage (v) 100 3032 g61 050 C15.300 C15.225 C15.150 C15.075 C15.000 C14.925 C14.850 C14.775 C14.700 C25 25 75 125 i l = C1ma
lt3032 series 8 3032fd typical performance characteristics lt3032-15 positive side gnd pin current inp voltage (v) 0 gnd pin current (ma) 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 16 3032 g68 4 2 6 10 14 18 8 12 20 t j = 25c v shdnp = v inp *for v outp = 15v r l = 100 *i l = 150ma r l = 150 *i l = 100ma r l = 300 *i l = 50ma lt3032-12 negative side gnd pin current inn voltage (v) 0 gnd pin current (ma) C3.0 C2.5 C2.0 C1.5 C1.0 C0.5 0 C16 3032 g67 C4 C2 C6 C10 C14 C18 C8 C12 C20 t j = 25c v shdnn = v inn *for v outn = C12v r l = 80 *i l = C150ma r l = 120 *i l = C100ma r l = 240 *i l = C50ma r l = 1.2k, *i l = C10ma lt3032-12 positive side gnd pin current inp voltage (v) 0 gnd pin current (ma) 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 16 3032 g66 4 2 6 10 14 18 8 12 20 t j = 25c v shdnp = v inp *for v outp = 12v r l = 80 *i l = 150ma r l = 120 *i l = 100ma r l = 240 *i l = 50ma lt3032-5 positive side gnd pin current lt3032-5 negative side gnd pin current inp voltage (v) 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 gnd pin current (ma) 3032 g56 0123 4 5 67 8910 r l = 33.3 i l = 150ma* r l = 50 i l = 100ma* r l = 100 i l = 50ma* t j = 25c v inp = v shdnp *for v outp = 5v inn voltage (v) C3.0 C2.5 C2.0 C1.5 C1.0 C0.5 0 3032 g57 gnd pin current (ma) 0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 t j = 25c v shdnn = v inn *for v outn = C5v r l = 33.3 i l = 150ma* r l = 50 i l = C100ma* r l = 100 i l = C50ma* r l = 500 i l = C10ma* lt3032 inp quiescent current inp voltage (v) 02 6 10 14 18 inp quiescent current (a) 30 25 20 15 10 5 0 4 8 12 16 3032 g09 20 t j = 25c r l = 250k v shdnp = v inp v shdnp = 0v lt3032-15 inn quiescent current lt3032-15 inp quiescent current inn voltage (v) 0 inn quiescent current (a) C80 C70 C60 C50 C40 C30 C20 C10 0 C16 3032 g65 C4 C2 C6 C10 C14 C18 C8 C12 C20 t j = 25c r l = v shdnn = 0v v shdnn = v inn inp voltage (v) 0 inp quiescent current (a) 400 350 300 250 200 150 100 50 0 16 3032 g64 4 2 6 10 14 18 8 12 20 t j = 25c r l = v shdnp = 0v v shdnp = v inp lt3032 inn quiescent current inn voltage (v) C40 C35 C30 C25 C20 C15 C10 C5 C0 3032 g10 inn quiescent current (a) 0 C2 C4 C6 C8 C10 C12 C14 C16 C18 C20 t j = 25c r l = 250k i l = C5a v shdnn = v inn v shdnn = 0v
lt3032 series 9 3032fd positive side gnd pin current vs i load negative side gnd pin current vs i load shdnp pin threshold shdnn pin thresholds shdnp pin input current shdnp pin input current lt3032 negative side gnd pin current C3.0 C2.5 C2.0 C1.5 C1.0 C0.5 0 3032 g12 gnd pin current (ma) 0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 r l = 12.2 i l = C100ma* r l = 24.4 i l = C50ma* r l = 122 i l = C10ma* t j = 25c; v shdnn = v inn ; *for v outn = C1.22v r l = 8.07 i l = C150ma* inn voltage (v) positive load current (ma) 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 gnd pin current (ma) 3032 g13 020 40 60 80 100 120 140 160 v inp = v outp(nominal) + 1v t j = 25c C4.0 C3.5 C3.0 C2.5 C2.0 C1.5 C1.0 C0.5 0 3032 g14 gnd pin current (ma) 0 C40 C60 C20 C80 C120 C140 C100 C160 v inn = v outn(nominal) C 1v t j = C50c t j = 25c t j = 125c negative load current (ma) temperature (c) C50 shdnp pin threshold (v) 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 50 75 3032 g15 C25 25 100 125 i l = 1ma on off 2.5 2.0 1.5 1.0 0.5 0 C0.5 C1.0 C1.5 C2.0 C2.5 3032 g16 shdnn pin voltage (v) on on off temperature (c) C50 C25 0 25 50 75 100 125 shdnp pin voltage (v) 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 shdnp pin input current (a) 3032 g17 0123 4 5 67 8910 temperature (c) C50 100 3032 g18 050 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 C25 25 75 125 shdnp pin input current (a) v shdnp = 20v typical performance characteristics lt3032 positive side gnd pin current inp voltage (v) 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 gnd pin current (ma) 3032 g11 0123 4 5 67 8910 r l = 8.07 i l = 150ma* r l = 12.2 i l = 100ma* r l = 24.4 i l = 50ma* t j = 25c v inp = v shdnp *for v outp = 1.22v lt3032-15 negative side gnd pin current inn voltage (v) 0 gnd pin current (ma) C3.0 C2.5 C2.0 C1.5 C1.0 C0.5 0 C16 3032 g69 C4 C2 C6 C10 C14 C18 C8 C12 C20 t j = 25c v shdnn = v inn *for v outn = C15v r l = 100 *i l = C150ma r l = 300, *i l = 50ma r l = 1.5k, *i l = C10ma r l = 150 *i l = C100ma
lt3032 series 10 3032fd typical performance characteristics negative side current limit reverse outp pin current temperature (c) C600 C500 C400 C300 C200 C100 0 3032 g26 negative side current limit (ma) C50 C25 0 25 50 75 100 125 v inn = C7v v outn = 0v outp pin voltage (v) 100 90 80 70 60 50 40 30 20 10 0 reverse outp pin current (a) 3032 g27 0246 8 10 12 14 16 18 20 t j = 25c, v inp = 0v current flows into outp pin v outp = v adjp (lt3032) lt3032 lt3032-5 lt3032-15 lt3032-12 negative side current limit inn-to-outn differential voltage (v) 0 C600 C500 C400 C300 C200 C100 0 3032 g25 C4 C8 C12 C16 C20 negative side current limit (ma) v outn = 100mv positive side current limit positive side current limit 500 450 400 350 300 250 200 150 100 50 0 inp-to-outp differential voltage (v) 0 positive side current limit (ma) 2 4 5 3032 g23 1 3 6 7 v outp = 0v 500 450 400 350 300 250 200 150 100 50 0 positive side current limit (ma) 3032 g24 v inp = 7v v outp = 0v temperature (c) C50 0 50 75 C25 25 100 125 shdnn pin input current 10 8 6 4 2 0 C2 C4 C6 C8 C10 3032 g19 shdnn pin input current (a) shdnn pin voltage (v) C10 C8 C6 C4 C2 0 2 4 6 810 t j = 25c positive current flows into the pin shdnn pin input current adjp pin bias current 12 9 6 3 0 C3 C6 C9 3032 g20 shdnn pin input current (a) temperature (c) C50 C25 0 25 50 75 100 125 v shdnn = 15v v shdnn = C15v v inn = C15v positive current flows into the pin temperature (c) C50 adjp pin bias current (na) 0 50 75 3032 g21 C25 25 100 125 140 120 100 80 60 40 20 0 adjn pin bias current C70 C60 C50 C40 C30 C20 C10 0 3032 g22 adjn pin bias current (na) temperature (c) C50 C25 0 25 50 75 100 125
lt3032 series 11 3032fd reverse outp pin current inp-to-outp ripple rejection inp-to-outp ripple rejection temperature (c) C50 reverse outp current (a) 45 40 35 30 25 20 15 10 5 0 0 50 75 3032 g28 C25 25 100 125 (lt3032-5) (lt3032-12/lt3032-15) (lt3032) v inp = 0v v outp = v adjp =1.22v (lt3032) v outp = 5v (lt3032-5) v outp = 12v (lt3032-12) v outp = 15v (lt3032-15) frequency (hz) inp-to-outp ripple rejection (db) 80 70 60 50 40 30 20 10 0 10 1k 10k 1m 3032 g29 100 100k i l = 150ma v inp = v outp(nominal) + 1.5v + 50mv rms ripple c bypp = 0 c outp = 2.2f c outp = 10f frequency (hz) inp-to-outp ripple rejection (db) 80 70 60 50 40 30 20 10 0 10 1k 10k 1m 3032 g30 100 100k i l = 150ma v inp = v outp(nominal) + 1.5v + 50mv rms ripple c outp = 10f c bypp = 0.01f c bypp = 100pf c bypp = 1000pf inn-to-outn ripple rejection 10 100 1k 10k 100k 1m frequency (hz) inn-to-outn ripple rejection (db) 80 70 60 50 40 30 20 10 0 3032 g31 i l = C150ma v inn = v outn(nominal) C 1.5v + 50mv rms ripple c bypn = 0 c outn = 10f c outn = 1f typical performance characteristics inp-to-outp ripple rejection inn-to-outn ripple rejection lt3032 minimum inp pin voltage lt3032 minimum inn pin voltage temperature (c) C50 inp-to-outp ripple rejection (db) 100 3032 g32 050 68 66 64 62 60 58 56 54 52 C25 25 75 125 v inp = v outp(nominal) + 1.5v + 0.5v p-p ripple at f = 120hz i l = 150ma temperature (c) 60 58 56 54 52 50 48 46 44 3032 g33 inn-to-outn ripple rejection (db) v inn = v outn(nominal) C 1.5v + 0.5v p-p ripple at f = 120hz i l = C150ma C50 C25 0 25 50 75 100 125 temperature (c) C50 minimum inp pin voltage (v) 0 50 75 3032 g34 C25 25 100 125 i l = 150ma 2.50 2.25 2.00 1.75 1.50 1.25 1.00 0.75 0.50 0.25 0 i l = 1ma v outp = 1.22v temperature (c) C3.0 C2.5 C2.0 C1.5 C1.0 C0.5 0 3032 g35 minimum inn pin voltage (v) i l = C150ma i l = C1ma C50 C25 0 25 50 75 100 125 note: the shdnn pin threshold must be met to ensure device operation positive load regulation temperature (c) 0 C10 C20 C30 C40 C50 C60 C70 3032 g36 load regulation (mv) C50 C25 0 25 50 75 100 125 v inp = v outp(nominal) +1v i l = 1ma to 150ma lt3032 lt3032-5 lt3032-12 lt3032-15
lt3032 series 12 3032fd typical performance characteristics outp 10hz to 100khz output noise c bypp = 0.01f 1ms/div c outp = 10f i l = 150ma v outp = 5v v outp 100v/div 3032 g45 outp 10hz to 100khz output noise c bypp = 0 1ms/div c outp = 10f i l = 150ma v outp = 5v v outp 100v/div 3032 g44 outn rms noise vs load current (10hz to 100khz) 140 120 100 80 60 40 20 0 load current (ma) outn rms noise (v rms ) C0.01 3032 g43 lt3032 lt3032-5 lt3032-12 lt3032-15 C1 C10 C1k C0.1 C100 c outn = 10f c bypn = 0 c bypn = 0.01f lt3032 lt3032-5 lt3032-12 lt3032-15 outn rms noise vs bypass capacitor c bypn (pf) 10 outn rms noise (v rms ) 250 200 150 100 50 0 100 1k 10k 3032 g42 c outn = 10f i l = C150ma f = 10hz to 100khz lt3032 lt3032-5 lt3032-15 lt3032-12 outp rms noise vs load current (10hz to 100khz) load current (ma) 0.01 outp rms noise (v rms ) 350 300 250 200 150 100 50 0 0.1 1 3032 g41 10 100 1k lt3032 lt3032-5 lt3032-12 lt3032-15 c outp = 10f c bypp = 0 c bypp = 0.01f lt3032 lt3032-5 lt3032-12 lt3032-15 negative load regulation outp noise spectral density temperature (c) 60 50 40 30 20 10 0 3032 g37 load regulation (mv) lt3032-5 lt3032-15 lt3032-12 lt3032 v inn = v outn(nominal) C 1v i l = C1ma to C150ma C50 C25 0 25 50 75 100 125 frequency (hz) 10 1k 10k 100k 3032 g38 100 10 1 0.1 0.01 outp noise spectral density (v/ hz ) c bypp = 1000pf c bypp = 100pf c outp = 10f i l = 150ma c bypp = 0.01f v outp = 5v v outp = v adjp outn noise spectral density frequency (hz) 0.1 outn noise spectral density (v/ hz ) 1 10 1k 10k 100k 3032 g39 0.01 100 10 c outn = 10f i l = C150ma c bypn = 1000pf c bypn = 0 v outn = C5v v outn = v adjn c bypn = 0.01f c bypn = 100pf outp rms noise vs bypass capacitor c bypp (pf) 10 outp rms noise (v rms ) 350 300 250 200 150 100 50 0 100 1k 10k 3032 g40 c outp = 10f i l = 150ma f = 10hz to 100khz lt3032 lt3032-5 lt3032-12 lt3032-15
lt3032 series 13 3032fd typical performance characteristics outn, 10hz to 100khz output noise, c bypn = 0 1ms/div c outn = 10f i load = C150ma v outn = C5v v outn 200v/div 3032 g46 outn, 10hz to 100khz output noise, c bypn = 0.01f outp transient response c bypp = 0 outp transient response c bypp = 0.01f v outn 100v/div 1ms/div c outn = 10f i load = C150ma v outn = C5v 3032 g47 time (s) 0.3 0.2 0.1 0 C0.1 C0.2 C0.3 outp voltage deviation (v) 150 100 50 0 load current (ma) 3032 g48 0 400 800 1200 1600 2000 v outp = 5v v inp = 6v c inp = 10f c outp = 10f time (s) 0.04 0.02 0 C0.02 C0.04 outp voltage deviation (v) 150 100 50 0 load current (ma) 3032 g49 040 80 120 160 200 v outp = 5v v inp = 6v c inp = 10f c outp = 10f outn transient response c bypn = 0 outn transient response c bypn = 0.01f time (s) 0.2 0.1 0 C0.2 C0.1 0 C50 C150 C100 outn voltage deviation (v) load current (ma) 3032 g50 0 100 200 300 400 500 600 700 800 900 1k v outn = C5v v inn = C6v c inn = 10f c outn = 10f time (s) 0.04 0.06 0.02 0 C0.02 C0.04 C0.06 C50 0 C100 C150 outn voltage deviation (v) load current (ma) 3032 g51 0 50 100 150 200 250 300 350 400 450 500 v outn = C5v v inn = C6v c inn = 10f c outn = 10f
lt3032 series 14 3032fd pin functions outp (pin 1): positive output. this output supplies power to the positive side load. a minimum output capacitor of 2.2f is required to prevent oscillations. larger out- put capacitors are required for applications with large transient loads to limit peak voltage transients. see the applications information section for more information on output capacitance, bypass capacitance, and reverse output characteristics. adjp (pin 2, adjustable part only): positive adjust. this is the input to the positive side error ampli? er. this pin is internally clamped to 7v. it has a typical bias current of 30na which ? ows into the pin (see curve of adjp pin bias current vs temperature in the typical performance characteristics). the adjp pin voltage is 1.22v referenced to ground and the output voltage range is 1.22v to 20v. bypp (pin 3): positive bypass. the bypp pin is used to bypass the reference of the positive side regulator to achieve low noise performance. the bypp pin is clamped internally to 0.6v (one v be ). a small capacitor from outp to this pin will bypass the reference to lower the output voltage noise. a maximum value of 0.01f is used for reducing output voltage noise to a typical 20v rms over the 10hz to 100khz bandwidth. if not used, this pin must be left unconnected. gnd (pins 4, 5, exposed pad pin 15): ground. one of the dfns exposed backside pads (pin 15) is an electrical connection to ground. to ensure proper electrical and thermal performance, solder pin 15 to the pcbs ground and tie directly to pins 4 and 5. connect the bottom of the positive and negative output voltage setting resistor dividers directly to pins 4 and 5 for optimum load regula- tion performance. inn (pin 6, 9, exposed pad pin 16): negative input. the dfn packages second exposed backside pad (pin 16) is an electrical connection to inn. to ensure proper electri- cal and thermal performance, solder pin 16 to the pcbs negative input supply and tie directly to pins 6 and 9. power is supplied to the negative side of the lt3032 through the inn pins. a bypass capacitor is required on this pin if it is more than six inches away from the main input ? lter capacitor. in general, the output impedance of a battery rises with frequency, so it is advisable to include a bypass capacitor in battery-powered circuits. a bypass capacitor in the range of 1f to 10f is suf? cient. outn (pin 7): negative output. this output supplies power to the negative side load. a minimum output capacitor of 1f is required to prevent oscillations. larger output capacitors are required for applications with large tran- sient loads to limit peak voltage transients. a parasitic diode exists between outn and inn; outn can not be pulled more negative than inn during normal operation, or more than 0.5v below inn during a fault condition. see the applications information section for more information on output capacitance and bypass capacitors. adjn (pin 8, adjustable part only): negative adjust. this is the input to the negative side error ampli? er. the adjn pin has a typical bias current of 30na that ? ows out of the pin. the adjn pin voltage is C1.22v referenced to ground, and the output voltage range is C1.22v to C20v. a parasitic diode exists between adjn and inn. the adjn pin cannot be pulled more negative than inn during normal operation, or more than 0.5v below inn during a fault condition. shdnn (pin 10): negative shutdown. the shdnn pin puts the negative side into a low power shutdown state. the shdnn pin is referenced to ground for regulator control, allowing the negative side to be driven by either positive or negative logic. the negative output will be off if the shdnn pin is within 0.8v(typical) of ground. pulling the shdnn pin more than C1.9v or +1.4v(typical) will turn the negative output on. the shdnn pin can be driven by 5v logic or open-collector logic with a pull-up resistor. the pull-up resistor is required to supply the pull-up current of the open-collector device, normally several microamperes, and the shdnn pin current, typically 3a out of the pin (for negative logic) or 6a into the pin (for positive logic). if unused, the shdnn pin must be connected to inn. the negative output will be shut down if the shdnn pin is open circuit. a parasitic diode exists between shdnn and inn, the shdnn pin cannot be pulled more negative than inn during normal operation, or more than 0.5v below inn during a fault condition.
lt3032 series 15 3032fd bypn (pin 11): negative bypass. the bypn pin is used to bypass the reference of the negative side regulator to achieve low noise performance. a small capacitor from outn to this pin will bypass the reference to lower the output voltage noise. a maximum value of 0.01f is used for reducing output voltage noise to a typical 30v rms over the 10hz to 100khz bandwidth. if not used, this pin must be left unconnected. shdnp (pin 12): positive shutdown. the shdnp pin puts the positive side into a low power shutdown state. the positive output will be off when the shdnp pin is pulled below 0.6v(typical). the shdnp pin can be driven by 5v logic or open-collector logic with a pull-up resistor. the pull-up resistor is required to supply the pull-up current of the open-collector device, normally several microam- peres, and the shdnp pin current, typically 1a into the pin. if unused, the shdnp pin must be connected to inp . pin functions the positive output will be shut down if the shdnp pin is open circuit. the shdnp pin can be tied directly to the shdnn pin and both pins driven directly by positive logic for a single point control of both outputs. nc (pin 13/pins 2, 8 for fixed voltage devices): no connect. the no connect pin has no connection to inter- nal circuitry and may be tied to inp , gnd, inn, shdnp , shdnn , outp , outn, ? oated, or tied to any other point. inp (pin 14): positive input. power is supplied to the positive side of the lt3032 through the inp pin. a bypass capacitor is required on this pin if it is more than six inches away from the main input ? lter capacitor. in general, the output impedance of a battery rises with frequency, so it is advisable to include a bypass capacitor in battery- powered circuits. a bypass capacitor in the range of 1f to 10f is suf? cient.
lt3032 series 16 3032fd the lt3032 is a dual 150ma positive and negative low noise low dropout linear regulator with micropower quiescent current and shutdown. it supplies 150ma at a dropout of 300mv. output voltage noise can be lowered on the positive side to 20v rms and to 30v rms on the negative side over the 10hz to 100khz bandwidth with the addition of 0.01f reference bypass capacitors. additionally, the reference bypass capacitors improve transient response, lowering the settling time for transient load conditions. quiescent current is 25a for the positive side and C30a for the negative side (45a each for the lt3032-12/ lt3032-15), typically dropping to less than 3a total in shutdown. in addition to the low quiescent current, the lt3032 incorporates several protection features which make it ideal for use in battery-powered systems. if the load is common mode between the two outputs, it does not matter which output starts ? rst; either output can be pulled to the opposing side of ground and the regulator will still start and operate. setting output voltage the adjustable lt3032 has output voltage ranges of 1.22v to 20v for the positive side and C1.22v to C20v for the negative side. the output voltages are set by the ratio of two external resistor dividers as shown in figure 1. the lt3032 servos the outputs to maintain the voltages at the adjp and adjn pins to 1.22v and C1.22v, respectively. the current in the bottom resistor of each divider (r1p or r1n) is equal to 1.22v/r1 and the current in the top resistor (r2p or r2n) is equal to the current in the bottom resistor plus the respective adjp/adjn pin bias current. the bias current for adjp and adjn is 30na at 25c, ? owing into the pin for adjp and ? owing out of the pin for adjn. the output voltages can then be calculated us- ing the formulas shown in figure 1. the value of r1p or r1n should be less than 250k to minimize errors in the resultant output voltage caused by the adjp/adjn pin bias current. note that in shutdown the respective output is turned off and the divider current will be zero. curves of adjp pin voltage, adjn pin voltage, adjp pin bias current, and adjn pin bias current (all vs temperature) appear in the typical performance characteristics. the lt3032 is tested and speci? ed with the adjp/adjn pin tied to the respective outp/outn pin and a 5a dc load (unless otherwise speci? ed) for an output voltage of 1.22v. speci? cations for output voltages greater than this will be proportional to 1.22v; (v out /1.22v). for example, load regulation for an output current change of 1ma to 150ma is C2mv typical at v outn = C1.22v. at v outn = C12v, load regulation is: (C12v/C1.22v)?(C2mv) = C19.6mv bypass capacitors and low noise performance the lt3032 provides reasonable noise performance without reference bypass capacitors from outp/outn to the corresponding bypp/bypn pin. using the lt3032 with the addition of reference bypass capacitors lowers output voltage noise. good quality low leakage capacitors are recommended. these capacitors bypass the internal references for the positive and negative sides of the lt3032, providing low frequency noise poles. the noise poles provided by the bypass capacitors decrease the output voltage noise to as low as 20v rms for the positive side and 30v rms for the negative side with the use of 0.01f bypass capacitors. the bypp pin and bypn pin are high impedance nodes and leakage into or out of these pins affects the reference voltage. the bypp pin operates at approximately 74mv at figure 1. setting output voltages applications information lt3032 outp v outp v outn r2p r1p r1n r2n adjp gnd adjn outn 3032 f01 + + v outp = 1.22v 1 + r2p r1p ? ? ? ? ? ? + i adjp () r2p () v adjp = 1.22v i adjp = 30na at 25 c output range = 1.22v to 20v v outn = C1.22v 1 + r2n r1n ? ? ? ? ? ? + i adjn () r2n () v adjn = C1.22v i adjn = C30na at 25 c output range = C1.22v to C 20v
lt3032 series 17 3032fd applications information 25c during normal operation where the bypn pin oper- ates at approximately C60mv. dc leakages on the order of 1a into or out of these pins can throw off the internal reference by 20% or more. output capacitance and transient response the lt3032 requires output capacitors for stability. it is designed to be stable with most low esr capacitors (typically ceramic, tantalum or low esr electrolytic). a minimum output capacitor of 2.2f with an esr of 3 or less is recommended to prevent oscillations on each output. the lt3032 is a micropower device and output transient response is a function of output capacitance. larger values of output capacitance decrease peak de- viations and provide improved transient response for larger load current changes. additional capacitors, used to decouple individual components powered by the lt3032, increase the effective output capacitor value. when using bypass capacitors (for low noise operation), larger values of output capacitors are needed. for 100pf of bypass ca- pacitance, 3.3f of output capacitance is recommended. with a 330pf bypass capacitor or larger, a 4.7f output capacitor is recommended. the shaded region of figure 2 de? nes the range over which the lt3032 is stable. the minimum esr needed is de? ned by the amount of bypass capacitance used, while the maximum esr is 3. these requirements are applicable to both the positive and nega- tive linear regulator. give extra consideration to the use of ceramic capacitors. ceramic capacitors are manufactured with a variety of di- electrics, each with different behavior across temperature and applied voltage. the most common dielectrics used are speci? ed with eia temperature characteristic codes of z5u, y5v, x5r and x7r. the z5u and y5v dielectrics are good for providing high capacitances in a small package, but they tend to have strong voltage and temperature coef? cients as shown in figures 3 and 4. when used with a 5v regulator, a 16v 10f y5v capacitor can exhibit an effective value as low as 1f to 2f for the dc bias voltage applied and over the operating temperature range. the x5r and x7r dielectrics result in more stable characteristics and are more suitable for use as the output capacitor. the x7r type has better stability across temperature, while the x5r is less expensive and is available in higher values. care still must be exercised when using x5r and x7r capacitors. the x5r and x7r codes only specify operating temperature range and maximum capacitance change over temperature. capacitance change due to dc bias with x5r and x7r capacitors is better than y5v and z5u capacitors, but can still be signi? cant enough to drop capacitor values below appropriate levels. capacitor dc bias characteristics tend to improve as component case size increases, but expected capacitance at operating voltage should be veri? ed in situ for a given application. voltage and temperature coef? cients are not the only sources of problems. some ceramic capacitors have a piezoelectric response. a piezoelectric device generates voltage across its terminals due to mechanical stress. in a ceramic capacitor, the stress can be induced by vibra- tions in the system or thermal transients. tapping on the ceramic bypass capacitor with a pencil generated the noise shown in figure 5. similar vibration induced behavior can masquerade as increased output voltage noise. output capacitance (f) 1 esr () 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 310 1762 f02 245 6 78 9 stable region c byp = 330pf c byp 3300pf c byp = 100pf c byp = 0 figure 2. stability
lt3032 series 18 3032fd stability and input capacitance low esr, ceramic input bypass capacitors are acceptable for applications without long input leads. however, applica- tions connecting a power supply to an lt3032s circuits inp/inn and gnd pins with long input wires combined with low esr, ceramic input capacitors are prone to voltage spikes, reliability concerns and application-speci? c board oscillations. the input wire inductance found in many battery-powered applications, combined with the low esr ceramic input capacitor, forms a high-q lc resonant tank circuit. in some instances this resonant frequency beats against the output current dependent ldo bandwidth and interferes with proper operation. simple circuit modi? ca- tions/solutions are then required. this behavior is not indicative of lt3032 instability, but is a common ceramic input bypass capacitor application issue. the self-inductance, or isolated inductance, of a wire is directly proportional to its length. wire diameter is not a major factor on its self-inductance. for example, the self- inductance of a 2-awg isolated wire (diameter = 0.26) is about half the self-inductance of a 30-awg wire (diameter = 0.01). one foot of 30-awg wire has about 465nh of self-inductance. one of two ways reduces a wires self-inductance. one method divides the current ? owing towards the lt3032 between two parallel conductors. in this case, the farther apart the wires are from each other, the more the self- inductance is reduced; up to a 50% reduction when placed a few inches apart. splitting the wires basically connects two equal inductors in parallel, but placing them in close proximity gives the wires mutual inductance adding to the self-inductance. the second and most effective way to reduce overall inductance is to place both forward and return current conductors (the input and gnd wires) in very close proximity. two 30-awg wires separated by only 0.02, used as forwardC and returnC current conductors, reduce the overall self-inductance to approximately one- ? fth that of a single isolated wire. applications information dc bias voltage (v) change in value (%) 3032 f03 20 0 C20 C40 C60 C80 C100 0 4 8 10 26 12 14 x5r y5v 16 both capacitors are 16v, 1210 case size, 10f figure 3. ceramic capacitor dc bias characteristics temperature (c) C50 40 20 0 C20 C40 C60 C80 C100 25 75 3032 f04 C25 0 50 100 125 y5v change in value (%) x5r both capacitors are 16v, 1210 case size, 10f figure 4. ceramic capacitor temperature characteristics output set to 5v 3032 f05 figure 5. noise resulting from tapping on a ceramic capacitor
lt3032 series 19 3032fd applications information if wiring modi? cations are not permissible for the applica- tions, including series resistance between the power supply and the input of the lt3032 also stabilizes the application. as little as 0.1 to 0.5, often less, is effective in damp- ing the lc resonance. if the added impedance between the power supply and the input is unacceptable, adding esr to the input capacitor also provides the necessary damping of the lc resonance. however, the required esr is generally higher than the series impedance required. thermal considerations the power handling capability of the device is limited by the maximum rated junction temperature (125c). the power dissipated by the device is made up of the follow- ing components: 1. output current of each side multiplied by the respective input/output voltage differential: (i out )(v in to v out ), and 2. gnd pin current for each side multiplied by its input voltage: (i gnd )(v in ) the gnd pin current of each side is found by examining the gnd pin current curves in the typical performance characteristics. total power dissipation equals the sum for both channels of the components listed above. the lt3032 has internal thermal limiting designed to pro- tect each side of the regulator during overload conditions. for continuous normal conditions, the maximum junction temperature rating of 125c must not be exceeded. it is important to give careful consideration to all sources of thermal resistance from junction to ambient. additional heat sources mounted nearby must also be considered. the lt3032 is a surface mount device and heat sinking is accomplished by using the heat spreading capabilities of the pc board and its copper traces. copper board stiffen- ers and plated through-holes can also be used to spread the heat generated by power devices. note that the exposed pads (pins 15 and 16) are elect- rically connected to ground (gnd) and the negative input (inn) respectively. the following table lists thermal resistance as a function of copper area on a ? xed board size. all measurements were taken in still air on a 4-layer fr-4 board with 1oz solid internal planes and 2oz external trace planes with a total ? nished board thickness of 1.6mm. table 3. de package, 14-lead dfn copper area board area thermal resistance (junction-to-ambient) topside* backside 2500mm 2 2500mm 2 2500mm 2 32c/w 1000mm 2 2500mm 2 2500mm 2 33c/w 225mm 2 2500mm 2 2500mm 2 38c/w 100mm 2 2500mm 2 2500mm 2 43c/w *device is mounted on topside for further information on thermal resistance and using thermal information, refer to jedec standard jesd51, notably jesd51-12. pcb layers, copper weight, board layout and thermal vias affect the resultant thermal resistance. this table provides thermal resistance numbers for best-case 4-layer boards with 1oz internal and 2oz external copper. modern, mul- tilayer pcbs may not be able to achieve quite the same level performance as found in this table.
lt3032 series 20 3032fd applications information calculating junction temperature example: given a positive output voltage of 3.3v, a posi- tive input voltage of 4v to 6v, output current range from 10ma to 150ma, negative output voltage of C3.3v, negative input voltage of C5v to C6v, a negative output current of C100ma, and a maximum ambient temperature of 50c, what will the maximum junction temperature be for a 2500mm 2 board with topside copper of 1000mm 2 ? the power in each side equals: p side = (v in(max) C v out )(i out(max) )+(v in(max) ?i gnd ) where, i outp(max) = 150ma v inp(max) = 6v i gnd at (i outp = 150ma, v inp = 6v) = 3.7ma i outn(max) = C100ma v inn(max) = C6v i gnd at (i outn = C100ma, v inn = C6v) = C1.5ma the total power equals: p total = p positive + p negative so, p positive = 150ma(6v C 3.3v) + 3.7ma(6v) = 0.43w p negative = C100ma(C6v+3.3v)C1.5ma(C6v) = 0.28w p total = 0.43w + 0.28w = 0.71w junction temperature equals: t j = t a + p total ? ja (using tables) t j = 50c + 0.71w ? 33c/w = 73.4c in this case, the junction temperature is below the maxi- mum rating, ensuring reliable operation. protection features the lt3032 incorporates several protection features that make it ideal for use in battery-powered circuits. in ad- dition to the normal protection features associated with monolithic regulators, such as current limiting and thermal limiting, the lt3032 is protected against reverse input voltages and reverse output voltages on both channels. current limit protection and thermal overload protection protect the device against current overload conditions at the outputs of the part. for normal operation, the junction temperature should not be allowed to exceed 125c. the positive input of the lt3032 withstands 20v reverse voltage. the negative input also withstands reverse volt- age, but the negative input may not be more than 0.5v (one v be ) higher than the outn and shdnn pins. this provides protection against batteries that are plugged in backwards. the outputs of the lt3032 can be pulled to opposing volt- ages without damaging the part. the outputs may be pulled to the opposing polarity with a load that is common mode between the two and one regulator starts before the other; in this condition, it does not matter which regulator started ? rst. both sides are capable of having the output pulled to the opposing polarity and both will still start and operate. if an input is left open circuit or grounded, the corre- sponding output can be pulled to its opposing polarity by as much as 20v. the output will act like an open circuit; no current will ? ow into or out of the pin. if the input is powered by a voltage source, the output will source the short-circuit current and will protect itself by thermal limiting. in this case, grounding the respective shdnp/ shdnn pin will turn off that side of the lt3032 and stop the output from sourcing current. the adjp pin can be pulled above or below ground by 7v without damage to the device. if the input is left open circuit or grounded, the adjp pin acts like an open circuit when pulled below ground and like a large resistor (typically 100k) in series with a diode when pulled above ground.
lt3032 series 21 3032fd applications information in situations where the adjp pin is connected to a resistor divider that would pull the adjp pin above its 7v clamp voltage if the output is pulled high, the adjp pin input current must be limited to less than 5ma. for example, a resistor divider is used to provide a 1.5v output from the 1.22v reference and the output is forced to 20v. the top resistor of the divider must be chosen to limit the current into the adjp pin to less than 5ma when the adjp pin is at 7v. the 13v difference between outp and adjp divided by the 5ma maximum current into the adjp pin yields a minimum top resistor value of 2.6k. in circuits where a backup battery is required on the posi- tive output, several different input/output conditions can occur. the output voltage may be held up while the input is either pulled to ground, pulled to some intermediate voltage or is left open circuit. current ? ow back into outp follows the curve shown in figure 6. if the inp pin is forced below the outp pin or the outp pin is pulled above the inp pin, input current typically drops to less than 2a. this can happen if the device is connected to a discharged (low voltage) battery and the output is held up by a backup battery or a second regula- tor circuit. the state of the shdnp pin has no effect on the reverse output current if outp is pulled above inp. figure 6. reverse output current outp pin voltage (v) 100 90 80 70 60 50 40 30 20 10 0 reverse outp pin current (a) 3032 f06 0246 8 10 12 14 16 18 20 t j = 25c, v inp = 0v current flows into outp pin v outp = v adjp (lt3032) lt3032 lt3032-5 lt3032-15 lt3032-12 like many ic power regulators, the negative side of the lt3032 has safe operating area (soa) protection. the safe operating area protection activates when the differential voltage between inn and outn is greater than -7v. the soa protection decreases current limit as a function of the voltage differential between inn and outn and keeps the power transistor inside a safe operating region for all values of forward input-to-output voltage. the protection is designed to provide some output current at all values of inn to outn differential voltage up to the absolute maximum rating. a 50a load is required to maintain regulation for inn to outn differential voltages greater than C7v. when in shutdown, protection circuitry remains active and will cause the output to rise slightly at zero load. a small pre-load is needed for zero output, if desired (see graph of quiescent current vs input voltage in typical performance characteristics). when power to the negative side is ? rst turned on, as the input voltage rises, outn follows inn, allowing the regula- tor to start into very heavy loads. during start-up, as the inn voltage is rising, the differential voltage between inn and outn is small, allowing the negative side to supply large output currents. with a high inn voltage, a problem can occur wherein removal of an output short will not al- low the output voltage to fully recover. other regulators, such as the lt1175, lt1964, and lt3080 also exhibit this phenomenon, so it is not unique to the lt3032. the problem occurs with a heavy output load when the inn voltage is high and the outn voltage is low. common situ- ations are immediately after the removal of a short-circuit or when the shdnn pin is pulled high after the inn pin has already been turned on. the load line for such a load may intersect the output current curve at two points. if this happens, there are two stable operating points for the negative side of the lt3032. with this double intersection, the inn supply may need to be cycled down to zero and brought up again to make outn recover.
lt3032 series 22 3032fd package description 3.00 p 0.10 (2 sides) 4.00 p 0.10 (2 sides) note: 1. drawing proposed is not a jedec package outline 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 p 0.10 1.65 p 0.10 1.65 p 0.10 bottom viewexposed pad 0.75 p 0.05 r = 0.115 typ r = 0.05 typ 3.00 ref 1 7 14 8 pin 1 top mark (see note 6) 0.200 ref 0.00 C 0.05 (de14ma) dfn 0507 rev a pin 1 notch r = 0.20 or 0.25 s 45 o chamfer 3.00 ref recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 2.10 p 0.05 0.70 p 0.05 3.50 p 0.05 package outline 0.25 p 0.05 0.25 p 0.05 0.50 bsc 1.78 p 0.10 0.10 typ 0.10 typ 1.07 p 0.10 1.07 p 0.05 0.51 typ 0.50 bsc 1.78 p 0.05 1.65 p 0.05 1.65 p 0.05 0.51 typ de14ma package 14-lead plastic dfn (4mm 3mm) (reference ltc dwg # 05-08-1731 rev a) please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
lt3032 series 23 3032fd information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number a 08/10 updated all applicable sections to add ? xed voltage 5v option. 1-7, 9-14 b 01/11 swapped outn and inn pins in absolute maximum ratings. revised values in shdnn and shdnp descriptions in pin functions. revised quiescent current for the positive side up to 25a in applications information. 2 12, 13 14 c 09/11 updated to add 12v and 15v options 1-12, 21 d 03/12 added mp-grade to order information and absolute maximum ratings 2, 3
lt3032 series 24 3032fd linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2010 lt 0312 rev d ? printed in usa related parts part number description comments lt1175 800ma negative low dropout micropower regulator v in : C 4.5v to -20v, i q = 45a, 0.5v dropout voltage, s8, dd-pak, to-220 and sot-223 packages LT1761 100ma, low noise ldo 300mv dropout voltage, low noise: 20v rms , v in = 1.8v to 20v, thinsot package lt1762 150ma, low noise ldo 300mv dropout voltage, low noise: 20v rms , v in = 1.8v to 20v, ms8 package ltc1844 150ma, very low dropout ldo 80mv dropout voltage, low noise <30v rms , v in = 1.6v to 6.5v, stable with 1f output capacitors, thinsot package lt1962 300ma, low noise ldo 270mv dropout voltage, low noise: 20v rms , v in = 1.8v to 20v, ms8 package lt1964 200ma, low noise, negative ldo 340mv dropout voltage, low noise 30v rms , v in = C1.8v to C20v, thinsot package lt3023 dual 100ma, low noise, micropower ldo v in : 1.8v to 20v, v out(min) = 1.22v, vdo = 0.30v, i q = 40a, isd < 1a; dfn and ms10e packages lt3024 dual 100ma/500ma, low noise, micropower ldo v in : 1.8v to 20v, v out(min) = 1.22v, vdo = 0.30v, i q = 60a, isd < 1a; dfn and tssop-16e packages lt3027 dual 100ma, low noise, micropower ldo with independent inputs v in : 1.8v to 20v, v out(min) = 1.22v, vdo = 0.30v, i q = 50a, isd < 1a; dfn and ms10e packages lt3028 dual 100ma/500ma, low noise, micropower ldo with independent inputs v in : 1.8v to 20v, v out(min) = 1.22v, vdo = 0.32v, i q = 60a, isd < 1a; dfn and tssop-16e packages lt3029 dual 500ma/500ma, low dropout, low noise, micropower linear regulator low noise: 20v rms (10hz to 100khz), low quiescent current: 55a per channel wide input voltage range: 1.8v to 20v (common or independent input supply) adjustable output: 1.215v reference, very low quiescent current in shutdown: <1a per channel stable with 3.3f minimum output capacitor, thermally enhanced 16-lead msop and 16-lead (4mm 3mm) dfn packages lt3082 200ma, parallelable, single resistor, low dropout linear regulator wide input voltage range: 1.2v to 40v low value input/output capacitors required: 0.22f, single resistor sets output voltage initial set pin current accuracy: 1%, low output noise: 40v rms (10hz to 100khz) reverse-battery protection, reverse-current protection 8-lead sot-23, 3-lead sot-223 and 8-lead 3mm 3mm dfn packages lt3032 inp 10f 10f 3032 ta02 536k 536k 95.3k 250k outp 5.5v to 20v C5.5v to C20v outn adjp bypp bypn adjn gnd shdnp shdnn 0.01f 0.01f 5v to 15v at 150ma C5v to C15v at C150ma on off 5v to 15v tracking supply typical application

▲Up To Search▲

Price & Availability of LT1761

	To Download LT1761 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .